1. Field of the Invention
The present invention relates to techniques for predicting instructions in a data processing apparatus, and in particular concerns such prediction in a data processing apparatus that supports multiple instruction sets.
2. Description of the Prior Art
A data processing apparatus will typically include a processor core for executing instructions. Typically, a prefetch unit will be provided for prefetching instructions from memory that are required by the processor core, with the aim of ensuring that the processor core has a steady stream of instructions to execute, thereby aiming to maximise the performance of the processor core.
To assist the prefetch unit in its task of retrieving instructions for the processor core, prediction logic is often provided for predicting which instruction should be prefetched by the prefetch unit. The prediction logic is useful since instruction sequences are often not stored in memory one after another, since software execution often involves changes in instruction flow that cause the processor core to move between different sections of code depending on the task being executed.
An example of a change in instruction flow that can occur when executing software is a “branch”, which results in the instruction flow jumping to a particular section of code as specified by the branch. Accordingly, the prediction logic can take the form of a branch prediction unit which is provided to predict whether a branch will be taken. If the branch prediction unit predicts that a branch will be taken, then it instructs the prefetch unit to retrieve the instruction that is specified by the branch, and clearly if the branch prediction is accurate, this will serve to increase the performance of the processor core since it will not need to stop its execution flow whilst that instruction is retrieved from memory. Typically, a record will be kept of the address of the instruction that would be required if the prediction made by the branch prediction logic was wrong, such that if the processor core subsequently determines that the prediction was wrong, the prefetch unit can then retrieve the required instruction.
When a data processor apparatus supports execution of more than one instruction set, this can often increase the complexity of the work to be performed by the prefetch unit and/or prediction logic. For example, U.S. Pat. No. 6,088,793 describes a microprocessor which is capable of executing both RISC type instructions and CISC type instructions. The RISC type instructions are executed directly by a RISC execution engine, and the CISC type instructions are first translated by a CISC front end into RISC type instructions for execution by the RISC execution engine. To facilitate higher speed operation when executing either RISC type instructions or CISC type instructions, both the CISC front end and the RISC execution engine include branch prediction units, which operate independent of one another. Further, CISC type instructions are converted into RISC type instructions in such a manner that mispredicted branches are easily identified by the branch behaviour of the resulting converted RISC type instructions.
Whilst U.S. Pat. No. 6,088,793 teaches the use of separate branch prediction units to maintain efficient prediction and hence increase microprocessor performance when supporting more than one instruction set, such an approach may not always be the most appropriate. For example, in U.S. Pat. No. 6,021,489, a technique is described for sharing a branch prediction unit in a microprocessor implementing a two instruction set architecture. This patent describes the use of a microprocessor that integrates both a 64 bit instruction architecture (Intel Architecture 64, or IA-64) and a 32 bit instruction architecture (Intel Architecture 32, or IA-32) on a single chip. However, with the aim of reducing the area of the chip, a shared branch prediction unit is provided which is coupled to separate instruction fetch units provided for each architecture.
Whilst the above patents illustrate that it is possible to predict changes in instruction flow, for example branch predictions, in a data processing apparatus that supports multiple instruction sets, the problem that still exists is how to efficiently switch between the multiple instruction sets. Accordingly, it is an object of the present invention to provide a technique which provides for efficient switching between instruction sets within a data processing apparatus that has a processor core for executing instructions from multiple instruction sets.